Phase lock loops typically have a phase detector for providing a control signal indicative of a phase difference between a reference signal and a feedback signal. A charge pump provides a voltage signal responsive to the control signal indicative of the phase difference. A voltage controlled oscillator (VCO) provides an oscillation signal responsive to the voltage signal. The voltage signal is fed back to the phase detector.
Conventional VCOs have multi-stage transconductors cascaded to form a ring. Theroretically, the number of transconductor stages required for sustainable oscillation is three or greater. Higher frequency VCOs use fewer number of stages. Many conventional VCOs, such as those described later herein in conjunction with FIGS. 2, 3 and 4 do not have supply rejection capability and thus are susceptible to supply noise induced jitter. Other conventional VCOs, such as that described later herein in conjunction with FIG. 5 have some level of supply rejection capability. Thermal noise induces intrinsic jitter in all VCOs. Intrinsic jitter may be reduced by using larger circuits which however also consume more power. On the other hand, intrinsic jitter levels of less than 5 picoseconds RMS are commonly achieved with relatively low power consumption. However, extrinsic jitter caused by noise on the supply is hard to control to less than 100 picoseconds. Hence, most designs address the extrinsic jitter of the VCO.
For high frequency operation, either the transconductance of each stage is increased (e.g., through increasing bias current) or the number of stages is reduced. For a given supply voltage, there is an upper limit by which the transconductance of the stage may be increased. This limit is typically reached in phase-lock loop VCOs. Conventional VCO designs must have at least three stages for the VCO to oscillate. If a quadrature output is required, the conventional VCO designs must have at least four stages thereby lowering the highest oscillation frequency.
It is an object of the invention to provide a VCO having two transconductor stages and providing both increased oscillation frequency and providing quadrature outputs.
It is an object of the invention to provide a VCO circuit with substantially higher level of supply rejection for lowering the jitter of the VCO.
Conventional charge pumps, such as that shown in FIG. 6 below, typically work accurately with fast switching characteristics at relatively high current levels, such as 15 microamps or larger. However, at lower charge pump currents and for shorter switching times, a charge injection error and a charge redistribution caused by non-zero parasitic capacitance becomes large relative to the intended charge to be delivered by the charge pump. In current sub-micron integrated circuit processes, the conventional charge pump of FIG. 6 becomes inaccurate for switching times of about 1 to 2 nanoseconds and at a current level of less than about 10 microamps. In applications that are sensitive to static phase error, such as a timing loop in a data recovery circuit in transmission or recording channels, the inability to provide low charge pump current accurately at high speed often results in phase lock loops having large loop filter capacitors. A static phase error is a constant error between the phase of the desired oscillation frequency and the frequency of the signal at which the phase-lock loop is locked. Such a static phase error may occur if the up and down portions of a charge pump are unbalanced. Such large filter capacitors increase the cost of the total circuit in monolithically integrated form. Furthermore, a large area capacitor has an adverse effect on the yield of monolithically integrated phase lock loops, which further exacerbates the manufacturing cost.
It is desirable to have a high frequency phase-lock loop with very low jitter and low static phase error for clock synchronizers. It is desirable to have a phase-lock loop with quadrature outputs for RF applications. It is also desired to provide an improved charge pump circuit that can operate accurately at very low current and high frequency and that allows inexpensive manufacturing of a complete phase lock loop.
In frequency synthesizers, the phase-lock loop circuit may use binary counters. Such circuits often have large transient supply noise that is created when a binary counter executes a major carry, such as from 00000000 to 11111111. It is desirable to have a phase-lock loop that disturbs the power supply to a lesser extent.